1. Field
Example embodiments relate to a semiconductor memory device, and more particularly, to a semiconductor memory device having dynamic memory cells without cell capacitors (hereinafter, referred to as “capacitorless dynamic memory cells”) and a method for operating the semiconductor memory device.
2. Description of Related Art
A unit memory cell of a dynamic random access memory (DRAM) is traditionally composed of one transistor and one capacitor. However, considering that the cell capacitor may act as a limit to scaling down a topological size of the memory device, there has been proposed a memory cell without a cell capacitor, which is called a “capacitorless memory cell,” simply having one transistor (1T) only. In such a 1T DRAM, a unit memory cell may include a body floated (i.e., electrically isolated) in the structure.
A general capacitorless memory may be fabricated on a silicon-on-insulator (SOI) wafer where silicon may be formed on an insulator, and senses data by accumulating majority carriers (holes or electrons) in a floating body or by releasing the majority carriers from the floating body. If majority carriers are accumulated in the floating body, it is represented as data “1.” On the other hand, if majority carriers are released from the floating body, it is represented as data “0.”
General capacitorless memory devices come in two types: one uses the characteristics of a metal-oxide-semiconductor (MOS); and the other uses the characteristics of a bipolar junction transistor (BJT). It is well known that the BJT is better than the MOS in high frequency operation and charge retention.